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[Other resource] 一些VHDL源代码

Description: 内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
Platform: | Size: 45110 | Author: 蔡孟颖 | Hits:

[VHDL-FPGA-Verilog] 一些VHDL源代码

Description: 内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
Platform: | Size: 45056 | Author: 蔡孟颖 | Hits:

[Other] prbs

Description: 伪随机序列产生器，VHDL程序，不记得在哪个论坛上下的。-Pseudo-random sequence generator, VHDL procedures, do not remember in which forum from top to bottom.
Platform: | Size: 2048 | Author: 韩丹 | Hits:

[assembly language] cmi

Description: 伪随机序列码发生器及基带传输CMI码编、译码的VHDL语言实现 -Pseudo-random sequence generator code and base-band transmission CMI code provision, decoding VHDL language
Platform: | Size: 179200 | Author: winnichan | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 伪随机序列发生器的vhdl算法 设计一个伪随机序列发生器，采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值（程序中设定好四种非零初值可选）。 -Pseudo-random sequence generator algorithm VHDL design of a pseudo-random sequence generator, using the generation polynomial for the 1+ X ^ 3+ X ^ 7. RESET has a client request and the two control registers client to adjust the initial value (procedures set of four non-zero initial value optional).
Platform: | Size: 1024 | Author: 文成 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 伪随机码发生器的VHDL实现 随着通信理论的发展，早在20世纪40年代，香农就曾指出，在某些情况下，为了实现最有效的通信，应采用具有白噪声的统计特性的信号。另外，为了实现高可靠的保密通信，也希望利用随机噪声。然而，利用随机噪声最大困难是它难以重复产生和处理。直到60年代，伪随机噪声的出现才使这一难题得到解决-Pseudo-random code generator for VHDL realize communication with the development of the theory, as early as the 20th century, 40 years, Shannon has pointed out that in some cases, in order to realize the most effective communications, should be used with the statistical properties of white noise signal . In addition, in order to realize highly reliable secure communication, but also wish to take advantage of random noise. However, the use of random noise the greatest difficulty is that it difficult to repeat the generation and treatment. Until 60 years, the emergence of pseudo-random noise so that this problem only be solved
Platform: | Size: 217088 | Author: 张之晗 | Hits:

[VHDL-FPGA-Verilog] fcsr

Description: 伪随机序列产生器－代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator- on behalf of binary feedback shift register, verilog hdl original code.
Platform: | Size: 1024 | Author: 李辛 | Hits:

[VHDL-FPGA-Verilog] pn127

Description: 这是个128位的串行伪随机码发生器，还可以进一步扩充-128 This is a serial pseudo-random code generator, can be further expanded
Platform: | Size: 446464 | Author: lee | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 8*8乘法器设计 伪随机序列发生器 PS2键盘设计 均为VHDL-8* 8 multiplier design of pseudo-random sequence generator are PS2 keyboard design VHDL
Platform: | Size: 2048 | Author: qiumh | Hits:

[Mathimatics-Numerical algorithms] random

Description: 伪随机数产生器,可以根据输入的控制字产生需要的伪随机数-Pseudo-random number generator
Platform: | Size: 2048 | Author: chengaj | Hits:

[source in ebook] weisuiji

Description: 伪随机比特发生器， VHdL写的伪随机比特发生器-Pseudo-random bit generator, pseudo-random bit generator, VHdL written in pseudo-random bit generator,
Platform: | Size: 1024 | Author: 阿道夫 | Hits:

[VHDL-FPGA-Verilog] wsjscsq

Description: VHDL程序设计的应用举例：伪随机数产生器-VHDL Programming Application examples: pseudo-random number generator
Platform: | Size: 7168 | Author: 古月 | Hits:

[Modem program] PRBS

Description: pseudo random bit sequence generator
Platform: | Size: 10240 | Author: sai | Hits:

[Windows Develop] LFSR

Description: verilog实现的8阶伪随机序列发生器，文件包含了三种主要模块：控制模块，ROM模块，线性反馈移位寄存器（LFSR）模块。已经通过modelsim仿真验证。-verilog to achieve 8-order pseudo-random sequence generator, the file contains three main modules: control module, ROM modules, a linear feedback shift register (LFSR) module. Has passed modelsim simulation.
Platform: | Size: 870400 | Author: 风影 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 伪随机序列发生器得VHDL语言源代码，已通过仿真。-Pseudo-random sequence generator may VHDL language source code, by simulation.
Platform: | Size: 2048 | Author: jacen | Hits:

[VHDL-FPGA-Verilog] VHDL-source-code

Description: 一些有用的VHDL代码 包括伪随机序列发生器等-VHDL code, including some useful pseudo-random sequence generator, etc.
Platform: | Size: 45056 | Author: yfgf | Hits:

[OS program] weisuiji

Description: 伪随机码系统器件发生器 产生伪随机序列 使用VHDL 语言开发设计，编写长度不长，只有20多行-Pseudo-random code system device generator produces pseudo-random sequence using VHDL language development and design, write the length is long, only 20 more lines
Platform: | Size: 23552 | Author: fanfan | Hits:

[VHDL-FPGA-Verilog] VHDL-simple-examples

Description: 上传的几个VHDL程序：分别是各种功能计数器；使用列举类型的状态机，四D触发器，通用寄存器，伪随机比特发生器，简单的状态机。-Upload several VHDL program: are the various functions of the counter using the enumerated type state machine, four D flip-flop, the general-purpose registers, pseudo-random bit generator, simple state machine.
Platform: | Size: 5120 | Author: 张俊 | Hits:

[File Format] vhdl

Description: 伪随机序列发生器的vhdl算法 设计一个伪随机序列发生器，采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值（程序中设定好四种非零初值可选）--Design of VHDL algorithm for pseudo random sequence generator is a pseudorandom sequence generator, using the generating polynomial 1+X^3+X^7. RESET has a client request and the two control registers client to adjust the initial value (procedures set of four non- zero initial value optional)
Platform: | Size: 1304576 | Author: 沙爽 | Hits:

[VHDL-FPGA-Verilog] pseudo-random-number-VHDL

Description: 伪随机序列发生器的vhdl软件，有m序列和gold序列的算法-pseudo random number generator
Platform: | Size: 46080 | Author: gone | Hits:
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